index - VLSI-SoC: Design Trends

Table of Contents
3D logic cells design and results based on Vertical NWFET technology including tied compact model *Mukherjee Chhandak, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu*
VLSI-SoC: Design Trends *Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Andre Reis*	Front Matter
Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI *David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot, Yohan Piccin*	1-19
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector *Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli*	21-37
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring *Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein*	39-63
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David Blaauw, Ronald Dreslinski Jr, Benton Calhoun, David D. Wentzloff	65-85
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform *Alessandro Veronesi, Davide Bertozzi, Milos Krstic*	87-112
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays *Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek*	113-131
Learning Based Timing Closure on Relative Timed Design *Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens*	133-148
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication *Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury*	149-178
From Informal Specifications to an ABV Framework for Industrial Firmware Verification *Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli*	179-204
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs *Matteo Sonza Reorda, Josie Condia*	205-233
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique *Jonas Gava, Ricardo Reis, Luciano Ost*	235-253
SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption *Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo*	255-278
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs *Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon*	279-300
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics *Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, Arijit Raychowdhury*	323-341
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory *Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky*	343-361

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